Catching Up


This morning, Battat and I met with Dr. Phillips about the project and I facilitated the meeting. We discussed:
  • Hardware update: divider circuit, decoder/demux, etc.
  • Delays in the glue logic and voltage diagram
  • Potential causes for the irregular counting and debugging methods
  • Muxes to ADC connection: Any barriers?
  • Determining the gain for op-amps
  • Next steps and plan for next week?
We decided to test the MUX/ADC connection with termination only at the sending end -- the MUX amplifier -- otherwise called "back-end termination." Doing such will help in that reflections from the ADC will be adequately absorbed in the termination and will not reflect to make a confounding signal at the ADC input. We will determine whether it actually works by using the ADC to measure the overshoot when switching channels and then use the findings in the decision regarding termination for the next prototype. What's more, we found that the ADS5292 demo board does not transmit direct current (DC) signals; according to the schematic, it contains transformers and blocking capacitors on the input lines, which prevent DC flow. However, we did choose to proceed with it as long as the ADC is capable of reproducing DC signals when installed on a future board. Important, open questions from the meeting include
  • Finding the equivalent input circuit for the ADC;
  • how to physically bring the ADC and Mux eval boards as close as possible, i.e. clip-on, lock-in mechanisms, etc;
  • and does the ADC reproduce DC signals?
We then discussed the plan for next week and onwards, as Battat is out the next week and Phillips will be around. Fortunately, I won't be left here completely alone, but I will have plenty to do according to the timeline we made:
  • July 7-11: Debug 4:1 mux and glue logic
  • " 14-18: Layout PCB for 8x(4x(4:1) mux and glue logic) --> ADC/FPGA eval boards too
  • " 21-25: Acquire PCB stuff... TEST
After the meeting, we shortly stepped into the lab to look at the counter and try to see some of the issues with the reading. Battat and Phillips both mentioned the irregular time durations for each SD and even the address lines. On the oscilloscope, however, the readings for the LSBs were incredibly skewed and it took us a good fifteen minutes to figure out that the issue lied in a broken channel and a defect cable.

Once we realized that, we discussed what days Phillips could come into the lab next week, how to order materials, what to accomplish bit by bit, etc. Having that plan in mind helped me see just how much further we need to go to get where we want to be and what we want others to see, hopefully, in a journal (and my poster).

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